1. Technical Field
The present invention generally relates to the cascode bias of power Metal Oxyde Semiconductor (MOS) transistors used e.g. in a power output stage of audio amplifier circuits.
It finds applications, in particular, in Integrated Circuits (IC) for wireless products such as mobile terminal devices (e.g. cell phones, smart phones, etc.), portable digital media players (e.g. MP3 and MP4 players), portable computers, wireless tablets, portable navigation systems, portable gaming devices, etc.
2. Related Art
The approaches described in this section could be pursued, but are not necessarily approaches that have been previously conceived or pursued. Therefore, unless otherwise indicated herein, the approaches described in this section are not prior art to the claims in this application and are not admitted to be prior art by inclusion in this section.
The need to deliver a wide range of multimedia services to users leads designers of wireless products to provide versatile, high-quality audio functions, including high-output power amplifier for driving e.g. hands-free speakers or earphones. To satisfy high quality user experience in media applications, the complexity of IC has strongly increased, pushing manufacturers to use deep submicron technology in order to integrate more and more complex applications.
Audio amplifiers have followed this trend, thus fulfilling in the same time the demand for high output power and high efficiency amplifiers. However, since the efficiency of the class AB amplifiers traditionally found in audio devices does not exceed 20-25% in most practical situations, a small increase in output power comes at the cost of a large increase in current consumption.
Class D amplifiers offer a potential solution to this challenge, achieving much higher efficiency than class AB amplifiers. In class D amplifiers, the output power may be controlled e.g. by Pulse Width Modulation (PWM). Operating on switching principles, rather than working with output transistors in linear mode, class D amplifiers can reach up to 95% of overall efficiency with a Total Harmonic Distortion (THD) comparable to that obtained with linear amplifiers.
To achieve in the same time high efficiency, high output power and high complexity of Digital Signal Processing (DSP) functions, the partitioning tends to integrate in the same chip some functions of the digital part (like DSP functions) along with circuits of the analog part (like D class audio amplifiers), using a deep submicron technology.
Deep submicron technology is very attractive for the implementation of digital processing units but appears to be very complicated for the design of analog, switched power amplifiers. One of the major difficulties is tied to its poor reliability, due to the thin oxide gate of the submicron technology. This causes also an increase of the consumption in quiescent mode of operation, because the gate capacitance is higher (given that the oxide thickness is much smaller).
In the application to D class amplifiers, power efficiency is however a key parameter for increased lifetime and enhanced user experience. For high output power, the weak point is the MOS resistivity (Rdson parameter) which generates conduction losses, while at low output power or in quiescent mode, the power losses are essentially due to capacitive switching.
To satisfy high output power demand without compromising the reliability of the analog part, designers may consider using extended drain MOS transistors, which can support higher voltage supply. The drawback of this solution is however the extra cost necessary to use special additional masks during the IC manufacturing process. Furthermore, the drain parasitic capacitance of an extended drain MOS transistor is higher than for a conventional MOS transistor, and thus the current consumption is increased.
Designers may also consider using some architectures which include cascoding MOS transistors to support the overall supply voltage. Such solution may be preferred to the extended drain MOS transistors solution, due to its non requirement of additional mask and thus its limited cost. The drawback of this solution, nevertheless, is the extra current consumption necessary to bias the cascode MOS transistors.
One solution for minimizing current consumption in low output power mode may be to segment the power stage into several parallel branches and to power down some branches in the low power mode. The problem is that the cascode MOS transistors must always be biased in order to maintain the reliability during output stage switching. Thus even if some branches are powered down, they consume a lot because of the capacitive switching losses of the cascode MOS transistors within these branches.
Reference [1] entitled “5.5-V I/O in a 2.5-V 0.25-μm CMOS Technology”, Anne-Johan Annema, Govert J. G. M. Geelen, and Peter C. de Jong, IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol. 36, No. 3, March 2001, discloses a high voltage tolerant, open-drain output circuit using thin oxide CMOS technology. It teaches an improvement to the classical single cascode output circuit architecture presented in FIG. 2a. The purpose is to implement an I/O circuit which tolerates supply voltages up to 5.5 V in a 2.5 V tolerant CMOS process using only baseline transistors running at a supply voltage of 2.5 V. This is achieved by using a plurality of stacked cascode transistors, thanks to some design tricks for driving the gate of the upper cascode transistor as shown in FIG. 3a with respect to a double-cascode architecture. Such design tricks include using a non-stationary gate voltage for one of the cascode transistors. However, the issue current consumption is not addressed by the teachings in this reference.